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Si4320
7. AFC Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
1
8
0
7
a1
6
a0
5
rl1
4
rl0
3
st
2
fi
1
oe
0
en
POR
C6F7h
Bit 0 ( en) enables the calculation of the offset frequency by the AFC circuit (it allows the addition of the content of the output register to the
frequency control word of the PLL).
Bit 1 ( oe ) when set, enables the output (frequency offset) register
Bit 2 ( fi ) when set, switches the circuit to high accuracy (fine) mode. In this case the processing time is about four times longer, but the
measurement uncertainty is less than half.
Bit 3 ( st ) strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the output registers of the AFC block.
Bit 4-5 ( rl0 , rl1 ) range limit: Limits the value of the frequency offset register to the following values:
rl1
0
0
1
1
rl0
0
1
0
1
Max dev [f res ]
No restriction
+15/-16
+7/-8
+3/-4
f res :
315, 433MHz bands: 2.5kHz
868MHz band: 5kHz
915MHz band: 7.5kHz
Bit 6-7 ( a0 , a1 ) Automatic operation mode selector:
a1
0
0
1
1
a0
0
1
0
1
Automatic operation mode
Auto mode off (Strobe is controlled by microcontroller)
Runs only once after each power-up
Drop the f offset value when the VDI signal is low
Keep the f offset value independently from the state of the VDI signal
15
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